The present invention relates to a semiconductor memory device and an apparatus to which the semiconductor memory device is applied. More particularly, the present invention relates to a semiconductor memory device that consumes less power, generates less noise, and provides a novel reading capability, as well as to an apparatus to which this semiconductor memory device is applied.
There is known a memory device having an address buffer, a row decoder, a column decoder, a column selector, a memory array, a read/write controller, a sense circuit, and an output buffer. An address signal is applied to the row decoder and the column decoder from the address buffer. A chip select signal is provided to the row decoder, the column decoder, and the read/write controller. When a specified memory cell in the memory array is selected based on the address signal and the chip select signal, a read signal coming from the memory cell is amplified by the sense circuit to be supplied to a load via the output buffer. In the above-mentioned memory circuit, the sense circuit is put in an inactive state after data has been read, thereby reducing the power consumption.
A problem with the conventional memory device is that, when the sense circuit goes from the active state to the inactive state, valid data can be read from the output buffer until a certain time elapses; but after this time has elapsed, the data read from the output buffer becomes invalid. That is, a variation in electric charge charged to a parasitic capacitance present in a circuit connecting the sense circuit and the output buffer makes an output level of the sense circuit be intermediate between a power supply potential and a reference potential. This may cause the output buffer to operate abnormally when the sense circuit is put in the inactive state, thereby causing a rush current to flow through the output buffer.
To solve the above-mentioned problem, an apparatus is proposed as disclosed in Japanese Patent Laid-open No. 4-82089, in which a circuit is provided to forcibly and fixedly set the output buffer level to a high level when the sense circuit goes into the inactive state. The proposed circuit setup can prevent the output level of the sense circuit from becoming the intermediate level, which in turn can prevent the abnormal current from flowing through the output buffer.
However, with the conventional technique, the output level of the output buffer is forcibly and fixedly set to the high level when the sense circuit goes from of the active state to the inactive state, so that a switching operation is required for fixing the output level to the high level. This switching operation may cause a power supply noise or a ground noise, thereby making the circuit operate erroneously. In addition, using the circuit having the above-mentioned setup for a memory device for multi-bit parallel output increases the power consumption due to the above-mentioned switching.
Further, with the conventional memory device, a read data valid time is assured only for a period as short as less than several nanoseconds when the memory device is put in a deselected state, so that there is a problem of restricting the availability of memory device utilizing techniques or the range of memory device applications.